Today, Icrontic serves up a crash-course in the mysterious relationship of the Core 2 front side bus, RAM and bandwidth. The nature of the Core 2′s design may be baffling, particularly to users exiting the era of synchronized Athlon XP buses, and we intend to cut through the haze and serve it straight just as we like to. Before we begin, however, there is a bit of background information that we will establish so we can quickly dispense with the rest of the juicy morsels.
A crash course in Intel’s bus architecture
Since the days of the Pentium 4, Intel has employed a bus technology known as Assisted Gunning Transceiver Logic+ (PDF), or AGTL+. AGTL+, and other logics like it, specifies how communication across your front side bus is to occur. Bus logic is now one of the most critical aspects of platform — that is, motherboard and chipset — development today. You may have heard that an Intel FSB is “Quad-pumped,” and this is all due to the AGTL+, which specifies that at twice the frequency of the FSB (FSB*2) you set in the BIOS, two transfers ((FSB*2)*2) occur as prompted by two “Strobes” that are 180° out of phase. We will come back to the “Quad pumped” notion later and dispel the myth it presents.
In the case of AGTL+, Intel specifies a reference voltage of 0.8v. A subtle shift of ±0.4v is enough to constitute “On” or “Off” to the AGTL+ logic, and more importantly, to trigger a transfer. A transfer is a transmission of an amount of data equal to the width of the front side bus
The width of the bus, often expressed in bits, indicates how much data can be moved across the bus per transfer. The Core 2′s bus width happens to be 64 bits, or 8 bytes wide. While 8 bytes doesn’t seem like very much, consider that one megahertz is one million hertz or cycles, and for every cycle of the FSB’s frequency, four transfers have occurred thanks to the nifty AGTL+ specification.