Intel’s new megahertz myth
At last, we can dispel a gigantic myth that plagues newcomers: The front side bus of your chip does not really have a quadruple-digit frequency. A more accurate figure would be the mega-transfer per second, or the MT/s, which is one million transfers. This is the case for information going over the FSB on an Intel platform where you have ((FSB*2)*2) mega-transfers per second.
To provide an example: Intel boasts that their Core 2s with a 266MHz FSB actually have a “1066MHz FSB!” It’s not wrong, but it’s not totally truthful either. We have established that one megahertz is one million cycles, so a 266.66MHz FSB must have 266,660,000 cycles. If we were to double that frequency to derive the AGTL+ frequency, we would get 533.32MHz or 533,320,000 cycles. As the rise of the clock and fall of the clock can both perform a transfer, that means we must multiply the AGTL+ frequency by two (533.32m*2) to get our final number of transfers per second, which is 1,066,640,000T/s. If we divide that number by one million to get MT/s instead of T/s, we come to our final figure of 1066MT/s. Doesn’t that 1066 number look oddly familiar?
Reconciling marketing with fact
Now that we have crushed one of the biggest myths that puzzle aspiring overclockers, let us move on to the morass that is the relationship between FSB, RAM and bandwidth. We have established that the ((FSB*2)*2) is the bandwidth on an Intel board’s bus, but how much of that is actually useable by the memory? What kind of bandwidth is offered by a certain frequency? Let us do another quick history lesson and sort it out.
In the days of SDRAM, a single clock cycle yielded a single transfer. Multiplying the speed of the RAM by the width of the bus indicated the amount of memory bandwidth available to the system. How were manufacturers going to reconcile the notion that their DDR, with two transfers per cycle, did double the workload of SDR at the same frequency? Their decision was obtuse but effective: If SDR did 133MT/s at 133MHz, and DDR did 266MT/s at 133MHz, then DDR should be advertised according to how many megahertz would be required of SDRAM to achieve the same result. The notion of doubling the actual frequency of the module to give it its “DDR Speed” was born. This antiquated idea has been carried forward to both DDR2 and DDR3.
Continuing in the legacy DDR had set, a 266MHz FSB became DDR2-533, a 400MHz FSB became DDR2-800 and so on. On the heels of the cycles versus transfers voodoo, marketers decided they would rate their memory modules according to the bandwidth offered by the DIMM. They computed this number as FSB*2*8, where the FSB is the raw cycles, two represents the transfers per cycle in DDR/DDR2/DDR3, and eight represents the width of the bus in bytes. Thus DDR2-533 became PC2-4200, DDR2-800 became PC2-6400 and so on. Whatever number follows PC-/PC2-/PC3- is the theoretical maximum bandwidth of the module in megabits per second at its stock frequency.
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