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Tilera building 100-core CPU

Tilera building 100-core CPU

The TILE-Gx block diagram

The TILE-Gx block diagram

Tilera Corporation has released some details on its current project, a 100-core central processing unit.

This chip is not to be confused with current graphics processors, which are already pushing 512 cores per chip. The processor Tilera is building is capable of running (a homegrown flavor of) Linux. The Tile-Gx100 uses an array of 10×10 cores linked with a mesh interconnect system dubbed “iMesh” and 256kb of L2 cache per core for a 26MB virtual L3 cache. The Tile-Gx100 processor will purportedly offer performance exceeding Intel’s forthcoming 8-core 16-thread Nehalem CPU “by a factor of four running Linux infrastructure workloads”.

The Tile-Gx100 is a 64-bit processor which will sport 4 on-chip DDR3 controllers capable of accessing up to 1TB of system memory. The processor will be offered in frequencies between 1.25GHz and 1.5GHz, and will cost as much as $1000 per chip in low volumes. Tilera also plans to offer several lower-end iterations on the design, including a 36-core version and a 16-core version.

It is interesting to observe that the Tile-Gx chips do not have a floating-point processor included on the die. For workloads requiring intense mathematical calculations, these processors would not likely fit the bill. However, in operations where math is not generally involved, the Tile-Gx series should offer excellent performance. With a maximum power consumption of 55w at full load, the Tile-Gx line is also very energy efficient.

These properties will likely make the Tile-Gx processors excellent for use in high-traffic web servers, database servers, and other such applications.


  1. Thrax
    Thrax Someone call me when they have an x86 license.
  2. Snarkasm
    Snarkasm They more than dodecatupled the number of cores... and only got a 4-fold increase in performance.
  3. Thrax
    Thrax Not surprising. Massively parallelized architectures don't use full execution engines for the cores... Some exclusive cache, an ALU, and a scheduler, and that's about it.

    The fact that the company hasn't published a block diagram of their cores is more telling than anything. It's probably build on the SPARCv9 or ARM ISA, and the lack of FPU makes it absolutely useless for any scientific applications. It also makes it impossible to measure in FLOPs.

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