Its been fun, but now, its time....
citrixmeta
Montreal, Quebec Icrontian
i have been running AMD for a few years now, But now its try new things.
here are the specs of my new rig.
INTEL PENTIUM 4 P4 2.6GHZ C 512K 800FSB S478 HT RETAIL BOX
ABIT IS7 S478 865PE ATX DUAL DDR AGP 5PCI SATA RAID 1394 SOUND LAN
CORSAIR TWINX512-3200LL PC3200 2X256MB DDR 2-3-2 SILVER HEAT SPREADER
r9700pro
bla bla.
HT enabled.
according to many reviews, i should be hitting 3.2ghz with this setup with a stock HSF
here are the specs of my new rig.
INTEL PENTIUM 4 P4 2.6GHZ C 512K 800FSB S478 HT RETAIL BOX
ABIT IS7 S478 865PE ATX DUAL DDR AGP 5PCI SATA RAID 1394 SOUND LAN
CORSAIR TWINX512-3200LL PC3200 2X256MB DDR 2-3-2 SILVER HEAT SPREADER
r9700pro
bla bla.
HT enabled.
according to many reviews, i should be hitting 3.2ghz with this setup with a stock HSF
0
Comments
TREASON! WITCH!
*cough*
Anyway, sounds good.
Though wouldnt a single 512MB stick be better than 2x256's? More expansion capability and its easier to hit higher speeds with a single stick as opposed to multiple sticks.... normally....
NS
let us know how you get on.
Craig
The 2 256's in this case (or 2 512's) would yeild DUAL Channel DDR SDRAM access with this board, one BANK per channnel not Dual Channel per stick so to speak. So, what was said for AMD is TRUE, but for this gen chipset with Intel and the 875p Intel chipset is false.
In this case, one stick yeilds single channel 512. Two sticks yeilds 256 per channel total 512 if each stick is on a separate channel. Sockets 1 and 3 and sockets 2 and 4 are in each channel, 1 and 4 or 2 and 3 or 1 and 2 would have one stick on each channel and I do not have a manual for that mobo to tell me which is best.
Since the CPU hyperthreads (the HT note in CPU spec) each pipe could use one channel for RAM this way. If speed for RAM is right, you then have two channels which each pump at FSB using PC3500 DDR RAM(not great, this is usually OC'd PC3200) or PC3700 DDR RAM(best). Each has one access on rise, one on fall. RDRAM can do 2 accesses per rise and 2 per fall with one bank, this strategy does one each per bank with channelized access so true simultaneous access can be done with 2 sticks where one is in each bank.
If I am wrong, someone please tell me what I misread in the Intel chipset specs, ok??? I am about 90%+ sure of all I wrote here.
John Danielson.
You think he has been hitting the juice gain Kanez?
Tex
The new P4's hyperthread, they have 2 processing pipes inside them. Either can use either channel for RAM. The CPU is wired and firmwared in such a way that each pipe uses the least busy RAM channel.
Now-- look at the sockets on the mobo-- they are in fact just DDR sockets. Each bank has an internal trace set for I\O (set of traces are what make up the channel), but the set of traces for each blank ends in different places when you look at the socket pinouts. The pipes can reach sither, but use usually only one at a time. So, software designed for hyperthreading can have one thread processed by one pipe and written to one bank of RAM while the second is writting to the second in Pentium 4 HT capable CPUs.
Beleieve me, I have in binders the tech specs for the Canterwood, the newer gen P4s, and Springdale chipsets.
Older ideas of banking were that you could only have X amount of RAM per bank, and extra banks were needed to let you have more RAM. CPUs could not write to multiple banks at once.
RDRAM was so expensive that people would not buy enough for Intel to makwe good volume profits, so engineering came up witht eh idea of letting multiple parts of RAM be written to at once-- one channel in use at one instant by each pipe, for two pipes. This eliminates the need for huge L1 and L2 cache, because it does not need to store what is waiting to go to RAM from one poipe while the other pipe is writting (even though that is fast).
The colors are not just for pretty, they are to deliniate distinct groups, or banks, of sockets.
Also, Base of FSB for the new HTs is 200. Not 166. While you can use older DDR you will getabottleneck doing so, and you get better overall performance if you minimioze the bottlenecks as much as possible so 200 MHz base Clock RAM is best to use. This calcs out to 3200 being minimal speed practical for reasonable flow and to overclock you need RAM that can run PC3700 NATIVELY.
IF this were not so, you woudl not need to have one stick in each bank on Intel Canterwood and Springdale boards. HALF of each stick would support each channel (as RDRAM does). But, the sockets are not that type, they are DDR sockets and DDR sockets do not have enough I\O traces to support two simultaneous channels of I\O.
RAM handling is one reason the new boards are not still 4 layers (My P4 Soyo Fire Dragon is a 4 layer board) if designed right, they have 6-8 LAYERS of conductivity. This means you can run the same number of traces per layer, and have RAM I\O channel traces run on different layers of traces (or conductive lines of metal in a layer).
RDRAM just accessed EACH stick twice as often. Each stick could read twice and write twice per clock cycle. DDR does not, by definition. It accesses one write and one read per clock cycle.
Sticks are still DDR, timed faster with faster reacting individual modules. The DDR blanks are not radically different in terms of wiring, only in terms of speed. The littler components are soldered to the same places as in older DDR. Each stick is a "single channel at a time" stick. Each bank is hooked to different place on CPU socket.
Addressing part of CORE tells each pipe output what channel to use at any one time. For 32 bit programs, one pipe is usually used perprogram-- thus the idea that FAH can run two instances on an HT core is valid, each program can use one pipe. But since each pipe has it own RAM if bnoth banks have RAM, they do not have to wait for each other to write to RAM because each has its own area to work with. There is less cache to RAM bottleneck this way. And twice as many traces means less heat than trying to force twice as many electrons through same traces.
Understand better???
John Danielson.
(who will be 50 in .45 years and first assembled a ZX81 and has built Pentiums, P4, K6-2 and Athlkon and Barton boxes and speced what goes in them)
With narrow neck bottle, you either carefully collapse ship and reassemble (and decrypting or unarchiving takes processor time) or cut off bottom carefully and then glue back on (which takes time, and cutting a trace breaks something).
Some mfrs wanted us to spend lots on cooling so they did not have to spend lots of money on making things much tinier so many more routes could be used to flow data. But we are on the edge of Moore's Laws about how much you can push through a limited space limiting how much we can do and the likelihood of Murphy intervening gets even better everytime you do something that brings Moore's Laws into play.
The goal of shrinking is not per se cooling, it is more traces or electrical paths per square inch so more can be done at once with less electricity per path and thus less heat per path. If enough less electricity per path is used, then you have same heat and more paths and better processing with less cooling needed.
This is why the HT P4s will want newer sockets with more pins (female) and why the much faster P4s will not need 3x the cooling. Lower voltages let you have less heat. Shorter distances let you use lower voltages. Tinier means shorter paths. Synergy of design results.
This is why Fab3 in Dresden Germany is retooling to use 90 nm process mfring of 130 nm for AMD. this is why Intel'schips get smaller per trace all the time. This is why motherboards and PCI cards can have more traces per cubic mm than before (more lower voltages inside mobo and core things). Thus, you can also now have baords of same or slightly thicker thickness as befor with 1.5 to 2X the number of layers. Thinner layers, more conductive metal, more traces and not 2X the heat.
Not only that,but the first prototypes arealmost never madetiny to exact size, because the way tech is progressing the designs will be mfr'd with smaller froms than the tests are and lower voltages can be used and thus less heat will come out of the actuals than the tests measure. Intel expected the P4s to run normally about 5-8 C above the temps they ARE running now when they were first prototyped.
The problem with tinier is things have to be more accurately made. Which means new tinier tools....
Since people can accept heat as major issue, that excuse is used. But issue is good parts yeilds percentages are not up to par yet for next gen of hardware or it would be in market now. And that is mostly tooling and mfring and design cross-checking and test bedding and computerized design evals.
Yeah, LIKE A FOX and I drink Caffein (CaffeinedIsMe might be an apt UID for me, or CAFFEINEDMe-- I also drink lots of Iced Coffee from an Acrylic cup (wide mouth, plastic insulates, coffee has lots of caffein).
John Danielson.
Nice rig, I'm sure you'll enjoy it.
I've seen some really nice 1u super micro machines with the 800 FSB and dual gig ether. The only thing that holds me back is waiting to see how the market fairs on 64bit AMD's.
I have literally a pile of AMD and intel's right now that I'm not using, but its just to much fun to take the latest hardware out and beat the snot out of it
Good luck!
my cpu should be coming in 2mmorow.
ill keep u guys updated.
Same cases as form factors for boards are not changed by CPU brand. Essentially, avoid an RDRAM motherboard and you can swap in sets the mothrboard and appropriate CPU.
John Danielson.
John Danielson.
Thankfully... this is why my laptop is still working