Bad_Karma said
The L1 is supposed to have 128 L1 cahce which is twice the tbred's cache, and maintaining the 256 L2 Cache.

ALL Athlons & Durons (Tbirds, Spitfires, Palys, Morgans, Tbreds, & Bartons) have 128K L1 Cache (64K Data + 64K Instruction = 128K L1 Total)

Using a Thorton core instead of a Tbred core means AMD only has to manufacture ONE Core instead of two. Bartons with Cache area defects become Thortons. All AMD has to do is deactivate the defective areas.

It's also how Intel makes it's Celeron Class CPUs....