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Intel 4MB Desktop CPU?!?

edited March 2004 in Science & Tech
[link=http://www.xbitlabs.com/news/cpu/display/20040316084519.html]XbitLabs: Intel Heads Towards 4MB Cache in Desktop Processors[/link]

[blockquote][link=http://pc.watch.impress.co.jp/docs/2004/0315/kaigai074.htm]PC Watch[/link] web-site claims that Intel’s code-named Merom microprocessor, which is also going to have a breed designed for desktop computers, will support all the latest techniques from Intel, including Intel Extended Memory 64 technology (IA32e), La Grande technology, Hyper-Threading technology, Vanderpool technology and some other features aimed to improve CPU performance and extend usage patterns of PC. The Merom microprocessor is expected to contain two or more processing cores and 4MB of built-in on-die cache, which is unbelievable size for desktop chips.

Processor code-named Merom was first mentioned as successor for Intel Pentium M CPU intended for mobile applications.

Merom and its desktop brother Conroe (2006) will be made using 65nm process technology and feature a new micro-architecture that will have a number of differences with NetBurst and Pentium M architectures used today. The architecture, though, will still be 32-bit in general.[/blockquote]

Comments

  • kanezfankanezfan sunny south florida Icrontian
    edited March 2004
    OK, I'm not up on my CPU knowledge so someone explain to me why they don't put more cache on CPUs to begin with. I'm sure it's a different type of memory than we use for system RAM, but if they just putting a lot more of it on a lot more CPUs, it would simply come down in price. anyone?
  • edited March 2004
    On die cache takes up a ton of room compared to the logic core. Processors with even a 2MB core dwarfs the size of the rest of a components on cpu's.

    KingFish
  • edited March 2004
    It's also running at full speed since it's on-die which means it's harder to make and more prone to failure.
  • JengoJengo Pasco, WA | USA
    edited March 2004
    wow, i wonder how they will perform??

    do you think faster then A64?

    hmmm...
  • mmonninmmonnin Centreville, VA
    edited March 2004
    Most likely it will be faster but its a long time away. No time soon. They dont have 90nm CPUs out let alone 65nm CPUs.

    Unless they make the core a lot bigger, 4MB will take up like 2/3 of the CPU core or around there somewhere. The 1MB cache is about half the size of the core now. So times that by 4 to get 4 MB.:)

    With the Pentium M, it is able to disable parts of the cache that is not in use. So that helps with power consumption and the reason they can have a lot more.

    pentiumm.jpg
  • shwaipshwaip bluffin' with my muffin Icrontian
    edited March 2004
    the cache gets slower as it gets bigger as well.
  • ginipigginipig OH, NOES
    edited March 2004
    I had questions, but they've been answered.
  • mmonninmmonnin Centreville, VA
    edited March 2004
    I dont think so shwaip. The cache runs at the same speed as the CPU MHz. For the P-M tho there are some added latencies in exchange for a LOT of saved power usage. Like the ability to turn of parts of the cache that is not used, there is a small latency to turn it back on and then write/read from it.

    I've read a few in-depth articles on the P-M the last week or so, so I can answer some more. It really is a marvel at what Intel has done with that chip.
  • shwaipshwaip bluffin' with my muffin Icrontian
    edited March 2004
    In one of my classes, computer architecture, we're learning about how to optimize processors for the best performance (pipelining, cache size, specialized components in the datapath), and the most recent lesson is on cache.

    Increasing the cache size causes fewer cache misses, however, the relationship is not 1:1. making the cache 4x as big reduces the miss ratio by ~1/2. In addition to these diminishing returns, as the cache gets larger, it becomes increasingly more difficult to access the cache in a single cycle, effectively defeating the purpose of having the cache.

    Also, like you said mmonnin, increasing the cache size would make the processor physically bigger, increasing the likelyhood that a single chip would have a defect in the silicon, and lowering the #/wafer, lowering yield.
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