Pipelining Explained

MediaManMediaMan Powered by loose parts.
edited May 2005 in Science & Tech
The word pipelining with respect to a processor may be a familiar word to enthusiasts but many may not know much beyond the term or even what it means. Learn now what pipelining is and if it is something that will benefit your computing experience or not.

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Comments

  • edited April 2004
    Greetings!!

    Nice, compact and informative article!

    Thank You!
  • Straight_ManStraight_Man Geeky, in my own way Naples, FL Icrontian
    edited April 2004
    One thing, differences between "pipe" and "pipelining" might be qualified in this way:

    Pipelining speaks to the strategies and tactics in design used in processing data into and through each pipe. HT-Capable CPUs that are also true multi-pipe (or multiple virtual CPUs on one die as we see it) will be seen as multiple CPUs to any O\S that is not HT-tuned and not 64 bit core.

    So if you see a CPU referred to as having two pipes or four or eight, it is multiple pipes. Pipelining is the throughput design expressed in L1 and\or L2 cache sizing(I include cahce as cache can be used for three things by a CPU, input, output, and very small amounts of pended work-- caching strategy is tightly tied to how a pipelining strategy works in reality), the instruction length of the pipe, and the bredth of the pipe (IE how many bits\word it uses natively), and how many steps each bit of a htread must go through to hit output side of pipe at CPU output.

    A well-designed multipipe CPU CAN process more than one O\S thread at the same time. Make it too long, what mediaman speaks of does happen-- threads get interrupted and even reset in part in mid thread sometimes if the pipe is too long as the pipe has to stop work while data and instructions trickle in too slowly and then resume. Too short, with high speed CPUs, RAM or cache gets overloaded (from output side of CPU pipe) and Windows then has to clear some more RAM and then the data that the CPU processes has to be written to HD (Virtual RAM or swap space on HD is used)while not actively in use.

    John D.
  • edited May 2005
    hi my name is miled from lebanon i wild ask about pipeline :how many stage there is like(fetch....)because my friend tel me about intel (20 stage)
    please tel me
    my email is bodium2002 at hotmail dot com
  • shwaipshwaip bluffin' with my muffin Icrontian
    edited May 2005
    Depends on the processor, but most architectures are comprised of the 5 basic stages that I wrote about in the article. Each stage can be broken into smaller substages to do "less" in a clock cycle. I can't tell you specifically what the stage names or what the individual stages accomplish in a given processor. My advice would be to use google to find the information. You could also check the white papers at intel's site (http://www.intel.com).

    It's unlikely that you'll find out exactly what is done in each stage, as this sort of thing is often considered a "trade secret". They don't want to release the information to the public, because that means that they release it to competitors (AMD, Via, whomever).
  • shwaipshwaip bluffin' with my muffin Icrontian
    edited May 2005
    actually...check out this xbit labs article...

    http://www.xbitlabs.com/articles/cpu/display/netburst-1_19.html
  • great help for me to understand the whole function.
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