Why is it when I see memory timings that some show 3 numbers and some show 4 numbers? For a while I though the fourth number was maybe the total number of clock cycles, but the first three always add up to more.
CAS:
CAS is Column Address Strobe or Column Address Select. CAS controls the amount of time (In cycles (2, 2.5, 3..)) between receiving a command, and acting on that command. Since CAS primarily controls the locating of HEX addresses, or memory columns, within the memory matrix, this is the most important timing to set as low as your system will stably accept it. There are both rows and columns inside a memory matrix. When the request is first electronically set on the memory pins, the first triggered response is tRAS (Active to Precharge Delay, see tRAS below). Data requested electronically is precharge, and the memory actually going to initiate RAS is activation. Once tRAS is active, RAS, or Row Address Strobe begins to find one half of the address for the required data. Once the row is located, tRCD (See tRCD below) is initiated, cycles out, and then the exact HEX location of the data required is accessed via CAS. The time between CAS start and CAS end is the CAS latency. Since CAS is the last stage in actually FINDING the proper data, it's the most important memory timing. This is somewhat like UPS finding your house. Your package doesn't do a damn bit of good at the central office if it can't get delivered quickly.
tRCD:
Also known as RAS to CAS delay, In addition to Column Address Strobe, there is Row Address Strobe (As described a bit above). CAS and RAS combined allow for the exact location of memory blocks. There is an interval between RAS (Activated when data is first requested) and CAS (Activated when RAS is complete), as memory can't locate a block precisely in a single stage. tRCD is the cycle time between the first stage in memory access, the row strobe, and the second stage, column strobe. However the performance impact of this setting is often neglible, as memory tries to store data from programs in sequential order. That is, it tries to keep the same row for a single program, and ordered columns to reduce the time for tRCD.
tRP:
Also known as RAS precharge, this is the amount of time it takes for memory to terminate the access in one row and begin another. Put simply, after data is set to the pins and activates tRAS, then RAS, then tRCD, then CAS, the memory needs to terminate its current row and start all over at tRAS. This is the very BASIC function of how memory works. This is only an important setting when you're doing massive shifting in data, like working with large virtual buffers, or video rendering. At that point, several rows are being consumed by a single program, and it's advantageous for the program to be able to switch quickly between these rows.
tRAS:
Also known as Active to Precharge delay, this is the time between receiving a request for data electronically on the pins of a memory module, and then initiating RAS to start the actual retrieval of data. This command seems important, but really isn't. Memory access is a very dynamic thing. Sometimes memory is being hit hard, and other times very sporadically. Though at all times, memory access is a constant, so it is rare that the tRAS command is received to access <i>new</i> data. A large shift.. Like opening a new program. Furthermore, this last timing often shows to be faster at 11 cycles than at 6 cycles on an nForce2 machine. Curious. No one knows, er, why.
Thank you, do you know if some motherboards show these labels as different labels? Or do some list more or less settings? And I think I am correct here, but don't a lot of sources actually put these settings in a different order sometimes? Sometimes especially I see the big number as the first one, would that mean the numbers are backwards or is just that one number misplaced.
Anyway, If anyone wants to help me, I'd like to attempt to OC some Corsair C2.0 XMS memory on a P4 system. I have one stick of 512mb pc3200. I am mostly concerned with what I should do first, second, and so on to test/oc the system. Note that I'd like to oc the fsb too and preferrably have a 1:1 ratio (if that's the best). Also note, when I have oc the fsb alone the frequency drops from 400 to 266 mhz for the ram after so much of an oc. I basically have never really touched the ram settings, but I did notice the default cas was 2.5 and I changed that to 2.0 without a problem or changing anything else, this being with or without a fsb oc.
If someone more has a list of what to do, or a good source that would be preferred, because I won't be able to fit too much testing in tonight (at least if my plans don't get interupted) for a post back and forth session every couple of minutes.
The minimum tRAS would be tRCD + CAS latency + 2 cycles, because if you set it any lower you'll be terminating access on something you need and starting over. Not good.
But by that formula 2 tRAS and 2 tRCD + 2 cycles = 6 tRAS is optimal, HOWEVER! Those 2 cycles are for a finite time of 100MHz according to Winbond whitepapers I've read, but when put to 200MHz like most of us are running, it becomes 2 tRAS + 2 tRCD + <b>4 cycles</b>.. Which is tRAS of 8, which still doesn't make any sense, but we're getting closer.
/me thinks aloud on this thread
I also have a theory. Since the minimum tRAS value, according to Winbond, is 40ns.. And our memory is pretty much all 5ns here, the tRAS has to control the ultimate achieving of the 40ns stable minimum.
So, for a second, let's replace those two cycles with a value that achieves 40ns for tRAS in accordance with the refresh of or DIMMs at 5ns.
2 tRAS + 2 tRCD + 6 = 10 tRAS, but that only satisfies 30ns (6*5).
So let's increase the value to 7.
2 tRAS + 2 trCD + 7 = 11 tRAS, 35ns (7*5). And that's getting a wee bit closer. Increase it to 8 cycles, and you've got a tRAS of 12 and supposedly an optimal setting.
Now, let's think for a minute that 40ns is recommended. A friendly level good for all memory parts, but some of us have sticks that are slightly better than the average DIMM.
35ns is quick! 2 tRAS + 2 tRCD + 7 = 11 sounds good, and meets the recommended tRAS in clock more or less according to Winbond.
So why does 6 work, when it only equals 30? Who knows. Out of spec works often in our world.. But perhaps because the ultimate tRAS of 11 is more "Ideal" it works better.
Thrax: I have tried convincing a lot of PIV users that Tras=5 is bad.
Guess what, they won't listen.
Often I recommend Tras=6 instead, but still they won't listen.
You know why? Because most of them thinks Tras=5 looks better in their signature. :banghead:
A lot of NF2 users doesn't understand Tras=11 either.
You have to slap two or three links in their face.
Then they might listen.
It is an uphill battle.
I'm glad that this community so readily understands the tRAS 11 bit. There's so many of us that, numerically speaking, we overwhelm people who were previously convinced of tRAS 5/6. It's nice.
Comments
I'm such a stinker!!!
CAS:
CAS is Column Address Strobe or Column Address Select. CAS controls the amount of time (In cycles (2, 2.5, 3..)) between receiving a command, and acting on that command. Since CAS primarily controls the locating of HEX addresses, or memory columns, within the memory matrix, this is the most important timing to set as low as your system will stably accept it. There are both rows and columns inside a memory matrix. When the request is first electronically set on the memory pins, the first triggered response is tRAS (Active to Precharge Delay, see tRAS below). Data requested electronically is precharge, and the memory actually going to initiate RAS is activation. Once tRAS is active, RAS, or Row Address Strobe begins to find one half of the address for the required data. Once the row is located, tRCD (See tRCD below) is initiated, cycles out, and then the exact HEX location of the data required is accessed via CAS. The time between CAS start and CAS end is the CAS latency. Since CAS is the last stage in actually FINDING the proper data, it's the most important memory timing. This is somewhat like UPS finding your house. Your package doesn't do a damn bit of good at the central office if it can't get delivered quickly.
tRCD:
Also known as RAS to CAS delay, In addition to Column Address Strobe, there is Row Address Strobe (As described a bit above). CAS and RAS combined allow for the exact location of memory blocks. There is an interval between RAS (Activated when data is first requested) and CAS (Activated when RAS is complete), as memory can't locate a block precisely in a single stage. tRCD is the cycle time between the first stage in memory access, the row strobe, and the second stage, column strobe. However the performance impact of this setting is often neglible, as memory tries to store data from programs in sequential order. That is, it tries to keep the same row for a single program, and ordered columns to reduce the time for tRCD.
tRP:
Also known as RAS precharge, this is the amount of time it takes for memory to terminate the access in one row and begin another. Put simply, after data is set to the pins and activates tRAS, then RAS, then tRCD, then CAS, the memory needs to terminate its current row and start all over at tRAS. This is the very BASIC function of how memory works. This is only an important setting when you're doing massive shifting in data, like working with large virtual buffers, or video rendering. At that point, several rows are being consumed by a single program, and it's advantageous for the program to be able to switch quickly between these rows.
tRAS:
Also known as Active to Precharge delay, this is the time between receiving a request for data electronically on the pins of a memory module, and then initiating RAS to start the actual retrieval of data. This command seems important, but really isn't. Memory access is a very dynamic thing. Sometimes memory is being hit hard, and other times very sporadically. Though at all times, memory access is a constant, so it is rare that the tRAS command is received to access <i>new</i> data. A large shift.. Like opening a new program. Furthermore, this last timing often shows to be faster at 11 cycles than at 6 cycles on an nForce2 machine. Curious. No one knows, er, why.
Anyway, If anyone wants to help me, I'd like to attempt to OC some Corsair C2.0 XMS memory on a P4 system. I have one stick of 512mb pc3200. I am mostly concerned with what I should do first, second, and so on to test/oc the system. Note that I'd like to oc the fsb too and preferrably have a 1:1 ratio (if that's the best). Also note, when I have oc the fsb alone the frequency drops from 400 to 266 mhz for the ram after so much of an oc. I basically have never really touched the ram settings, but I did notice the default cas was 2.5 and I changed that to 2.0 without a problem or changing anything else, this being with or without a fsb oc.
If someone more has a list of what to do, or a good source that would be preferred, because I won't be able to fit too much testing in tonight (at least if my plans don't get interupted) for a post back and forth session every couple of minutes.
The minimum tRAS would be tRCD + CAS latency + 2 cycles, because if you set it any lower you'll be terminating access on something you need and starting over. Not good.
But by that formula 2 tRAS and 2 tRCD + 2 cycles = 6 tRAS is optimal, HOWEVER! Those 2 cycles are for a finite time of 100MHz according to Winbond whitepapers I've read, but when put to 200MHz like most of us are running, it becomes 2 tRAS + 2 tRCD + <b>4 cycles</b>.. Which is tRAS of 8, which still doesn't make any sense, but we're getting closer.
/me thinks aloud on this thread
I also have a theory. Since the minimum tRAS value, according to Winbond, is 40ns.. And our memory is pretty much all 5ns here, the tRAS has to control the ultimate achieving of the 40ns stable minimum.
So, for a second, let's replace those two cycles with a value that achieves 40ns for tRAS in accordance with the refresh of or DIMMs at 5ns.
2 tRAS + 2 tRCD + 6 = 10 tRAS, but that only satisfies 30ns (6*5).
So let's increase the value to 7.
2 tRAS + 2 trCD + 7 = 11 tRAS, 35ns (7*5). And that's getting a wee bit closer. Increase it to 8 cycles, and you've got a tRAS of 12 and supposedly an optimal setting.
Now, let's think for a minute that 40ns is recommended. A friendly level good for all memory parts, but some of us have sticks that are slightly better than the average DIMM.
35ns is quick! 2 tRAS + 2 tRCD + 7 = 11 sounds good, and meets the recommended tRAS in clock more or less according to Winbond.
So why does 6 work, when it only equals 30? Who knows. Out of spec works often in our world.. But perhaps because the ultimate tRAS of 11 is more "Ideal" it works better.
Guess what, they won't listen.
Often I recommend Tras=6 instead, but still they won't listen.
You know why? Because most of them thinks Tras=5 looks better in their signature. :banghead:
A lot of NF2 users doesn't understand Tras=11 either.
You have to slap two or three links in their face.
Then they might listen.
It is an uphill battle.