Athlon 64 Pins & Needles (Thoughts about Why the Multiple Sockets)
Omega65
Philadelphia, Pa
<a href="http://www.theinquirer.net/?article=10954" target=_blank>The Inq: Athlon 64 Pins & Needles (Thought about Why the Multiple Sockets)</a>
<i>
The problem now is that AMD is faced with having its flagship consumer CPU saddled with slow, expensive, hard to find RAM, and it can't fix it without a major redesign. There are two memory controllers on the Opteron based chips, and one on the Athlon64 non-FX line. The controllers can act in concert, or separately, depending on a lot of things. It seems that AMD has chosen to implement them in concert on the current Opterons, so you must add DIMMs in pairs. This means you can have two or four DIMMS per chip. If you use DDR400, as everyone will on the Athon64s, and it can support three DIMMS, you are artificially capped at two DIMMS. Since both are necessary to start with, there is no expandability without throwing DIMMs away. Not good.
The way to solve this problem is to split up the memory controllers to act in two channels of 64 bits instead of one 128 bit channel. This would effectively halve the number of individual chips that need a clock signal sent to them, allowing for three or four DIMMs per channel, most likely three. Best of both worlds, so why doesn't AMD implement this at the Athlon64 launch in a month or so? Simple, it didn't connect the pins for the clock distribution of the second channel. To fix this, all it needs to do, is redo the Opteron package, make all new motherboards, and convince everyone not to use the old chip in the new boards, and vice-versa, easy enough.
So, why isn't it doing that? Well, it doesn't need to for servers, they require the more expensive RAM for the ECC side of things, Registration and Buffering don't really add to the cost that much, so they don't save anything, and lose a bit for the high end, high profit machines. Catch-22. How do you solve this? Enter socket 939.</i>
<a href="http://www.theinquirer.net/?article=10954" target=_blank>much more here!</a>
<i>
The problem now is that AMD is faced with having its flagship consumer CPU saddled with slow, expensive, hard to find RAM, and it can't fix it without a major redesign. There are two memory controllers on the Opteron based chips, and one on the Athlon64 non-FX line. The controllers can act in concert, or separately, depending on a lot of things. It seems that AMD has chosen to implement them in concert on the current Opterons, so you must add DIMMs in pairs. This means you can have two or four DIMMS per chip. If you use DDR400, as everyone will on the Athon64s, and it can support three DIMMS, you are artificially capped at two DIMMS. Since both are necessary to start with, there is no expandability without throwing DIMMs away. Not good.
The way to solve this problem is to split up the memory controllers to act in two channels of 64 bits instead of one 128 bit channel. This would effectively halve the number of individual chips that need a clock signal sent to them, allowing for three or four DIMMs per channel, most likely three. Best of both worlds, so why doesn't AMD implement this at the Athlon64 launch in a month or so? Simple, it didn't connect the pins for the clock distribution of the second channel. To fix this, all it needs to do, is redo the Opteron package, make all new motherboards, and convince everyone not to use the old chip in the new boards, and vice-versa, easy enough.
So, why isn't it doing that? Well, it doesn't need to for servers, they require the more expensive RAM for the ECC side of things, Registration and Buffering don't really add to the cost that much, so they don't save anything, and lose a bit for the high end, high profit machines. Catch-22. How do you solve this? Enter socket 939.</i>
<a href="http://www.theinquirer.net/?article=10954" target=_blank>much more here!</a>
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