Intel Preps 3.50GHz Server Chips With 8MB Cache

KingFish

Leading chipmaker Intel Corp. has unwrapped some of its plans concerning the server and workstation processors and chipsets. The main headliners of Intel’s pedestal and rack server roadmap – Intel Xeon MP processor code-named Potomac and Intel’s dual-core chip code-named Smithfield – finally got their target clock-speeds and cache sizes from Intel’s official documents.

Intel’s Xeon processor family for multiprocessor (MP) applications will finally be updated in Q1 2005 with chips code-named Cranford that contain 1MB of L2 cache, but operate at 3.66GHz, much higher than today’s 3.0GHz. In server environments clock-speed does not necessarily mean performance crown, as server software is seriously dependant on cache size and from that perspective Intel’s Xeon MP 3.0GHz with 4MB L3 cache may be a better choice for certain types of server deployments. Still, the processors code-named Cranford are to be made using 90nm process technology, which may allow Intel Corp. to set a bit lower prices on such products compared to previously released Intel Xeon MP processors at launch.

In the second quarter Intel Corp. is projected to release its highly-anticipated Intel Xeon multiprocessing unit (MPU) code-named Potomac that is positioned as a high-end offering for MP servers. Potomac chips will operate at speeds of 3.50GHz or higher and contain up to 8MB of level-three cache in addition to 1MB of L2 cache. Potomac will also be produced using 90nm process technology.

Both Cranford and Potomac are expected to feature Enhanced Memory 64 Technology (EM64T) as well as Executed Disable Bit (EDB) security feature. The chips will operate using 667MHz Quad Pumped Bus and use Intel’s Twin Castle chipset.

Source: X-Bit Labs

muddocktor

I bet they'll chew the power up too. Maybe the datacenters will have to start adding a wattage surcharge on these critters when they start getting deployed to help pay for upgrading the cooling systems in their server rooms.