Clock Implementation in VHDL

edited March 2005 in Internet & Media
Can anyone tell me how do I implement an external clock in my design.
I have statements like 'wait for 200ns' etc in my code. How does the compiler calculate this delay. Which statements must I specify in my code to tell the compiler that I'm using a 10Mhz crystal clock in my design.

I'm working on a 9536 CPLD and using the Webpack ISE software by Xilinx.

Thank you.

Riberet
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