Clock Implementation in VHDL
Can anyone tell me how do I implement an external clock in my design.
I have statements like 'wait for 200ns' etc in my code. How does the compiler calculate this delay. Which statements must I specify in my code to tell the compiler that I'm using a 10Mhz crystal clock in my design.
I'm working on a 9536 CPLD and using the Webpack ISE software by Xilinx.
Thank you.
Riberet
I have statements like 'wait for 200ns' etc in my code. How does the compiler calculate this delay. Which statements must I specify in my code to tell the compiler that I'm using a 10Mhz crystal clock in my design.
I'm working on a 9536 CPLD and using the Webpack ISE software by Xilinx.
Thank you.
Riberet
0