Prescott (Pentium 5?) Info

Omega65Omega65 Philadelphia, Pa
edited September 2003 in Science & Tech
    * 90nm micron process * 112mm2 Die Size * 125M Transistors *
Thermal Design Power - 103W
* 800Mhz FSB
* 1MB L2 Cache / 16KB L1 Cache
* SSE-3
* 13 Prescott New Instructions (PNI)
* Longer Pipelines
* Enhanced Hyper-Threading
* Improved pre-fetch branch predictions
* Improved Integer Multiply latency
* Improved Power management.
* Additional Write Combining buffers
* Reduce clock skew across die with a new clock distribution scheme
* La Grande Technology is present but software support will come later
* Socket 478 - Q4 '03,
* Socket T LGA 775 - H2 2004
* Availability : 3.2 & 3.4Ghz in Oct 2003, 3.6Ghz - Q1 '04, 3.8Ghz - Q2 '04
* Pricing : 3.2Ghz - $278, 3.4Ghz - $417, 3.6Ghz - 637, 3.8Ghz - $637


Source : VR-Zone

Comments

  • TheBaronTheBaron Austin, TX
    edited September 2003
    i see some things i like, some things i dont. i like the improved latency, maybe that'll help get their ipc up
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited September 2003
    * 90nm micron process
    Good to see
    * 112mm2 Die Size
    Only 3mm^2 smaller than the Athlon 64 and it's .09? Hmph.
    * Thermal Design Power - 103W
    Ew?
    * 800Mhz FSB
    Doesn't mean a whole lot any more! Thanks AMD!
    * 1MB L2 Cache / 16KB L1 Cache
    Talk about being late to the party. Still only 16kb L1? Lame.
    * SSE-3
    Yay! More features to dupe consumers and serve no purpose for 12 months!
    * 13 Prescott New Instructions (PNI)
    I wish they would elaborate.
    * Longer Pipelines
    <b>JUST</b> what the Pentium series needs!
    * Enhanced Hyper-Threading
    Capitalizing on their previous implementation of Hyperthreading, Intel has vowed to make more programs slower than ever before.
    * Improved pre-fetch branch predictions
    It better be improved with longer pipelines.
    * Improved Integer Multiply latency
    Atleast it can actually multiply now. The Northwoods actually couldn't. But I still don't see a power FPU until they completely redo the one they have or steal AMD's.
    * Improved Power management.
    90 Amps through the motherboard traces and 103w of radiate heat, and that's improved power management? In comparison to what? A battery-powered generator?

    I'm spent. New sockets for Intel users, huzzzzzaaaaah.
  • a2jfreaka2jfreak Houston, TX Member
    edited September 2003
    I agree with Thrax on some things, and disagree on others:
    Thrax said
    * 90nm micron process
    Good to see

    Agreed!
    * 112mm2 Die Size
    Only 3mm^2 smaller than the Athlon 64 and it's .09? Hmph.

    More transistors, but one would think a 90nm process would bring the size down more.
    * Thermal Design Power - 103W
    Ew?

    Agreed!
    * 800Mhz FSB
    Doesn't mean a whole lot any more! Thanks AMD!

    Agreed!
    * 1MB L2 Cache / 16KB L1 Cache
    Talk about being late to the party. Still only 16kb L1? Lame.

    Thankfully it is only 16KB, as Intel uses anInclusive L2 so everything in the L1 is replicated in the L2, so 1024KB - 16KB leaves a lot more L2 than if the L1 were 64KB or 128KB. AMD uses an Exclusive cache, which means 1024KB of L2 is actually 1024KB of L2.
    * SSE-3
    Yay! More features to dupe consumers and serve no purpose for 12 months!

    Yes/No. The extra instructions allow for more efficienct use of the CPU, but you're correct that it won't benefit the user for a while, and also how many extension is Intel/AMD going to add to X86 before they drop it?
    * 13 Prescott New Instructions (PNI)
    I wish they would elaborate.

    They have.
    * Longer Pipelines
    <b>JUST</b> what the Pentium series needs!

    To scale in clock (which is what the p4 needs) it has to have a deeper pipeline, so this actually is JUST (part of) what the Pentium series needs.
    * Enhanced Hyper-Threading
    Capitalizing on their previous implementation of Hyperthreading, Intel has vowed to make more programs slower than ever before.

    For some things it is better, for others it's worse. Most of the time I think people benefit from HT, but there are definite times when HT turns the chip into a slug.
    * Improved pre-fetch branch predictions
    It better be improved with longer pipelines.

    Amen!
    * Improved Integer Multiply latency
    Atleast it can actually multiply now. The Northwoods actually couldn't. But I still don't see a power FPU until they completely redo the one they have or steal AMD's.

    ALU hasn't a huge issue for the p4 IIRC.
    * Improved Power management.
    90 Amps through the motherboard traces and 103w of radiate heat, and that's improved power management? In comparison to what? A battery-powered generator?

    90 amps is a bit much, but I don't think it's going to be much of an issue when you consider new boards are going to be designed for the Prescott so the traces can be made to withstand more juice.
    I'm spent. New sockets for Intel users, huzzzzzaaaaah.

    New sockets for AMD users too with the AMD64 line of processors, but I think I know what you mean.

    AMD is changing socket because it's going from the K7 to the K8. Intel is changing socket mid-stream. What Intel is doing is about like if AMD had changed sockets between the TBird and the Palomino. (We did get a Slot-A to Socket-A change, but that was early on and I'll forgive AMD for that because Intel did the same thing with the p3, plus I think socket CPUs are better for the overclockers)
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited September 2003
    A longer pipeline continues to add to the gross inefficiencies that are Intel processors. Such also increases the possibility of calculation errors, decreases instructions per cycle, and generally allows AMD to get more done on a slower clockspeed which is what Intel should be avoiding.
  • Park_7677Park_7677 Missouri Member
    edited September 2003
    Thrax said
    A longer pipeline continues to add the gross inefficiencies that are Intel processors. Such also increases the possibility of calculation errors, decreases instructions per cycle, and generally allows AMD to get more done on a slower clockspeed which is what Intel should be avoiding.


    Amen!

    I laughed when I read of the longer pipelines! Well.. I really laughed at most of the specs really... ;D
  • a2jfreaka2jfreak Houston, TX Member
    edited September 2003
    Thrax said
    A longer pipeline continues to add to the gross inefficiencies that are Intel processors. Such also increases the possibility of calculation errors, decreases instructions per cycle, and generally allows AMD to get more done on a slower clockspeed which is what Intel should be avoiding.

    I wasn't stating that I think long pipelines are necessarily a good thing, but unfortunately the architecture of the p4 requires such.

    Like you, I think a higher IPC is better than higher MHz. Eventually Intel is going to hit a wall w/ the MHz, where AMD can keep going. Sure, Intel could increase the IPC on the chip, but that would be a MAJOR rework, whereas AMD would just need to refine the process and make must less drastic changes to achieve higher clock speeds.
  • GHoosdumGHoosdum Icrontian
    edited September 2003
    Amen, brother.
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited September 2003
    ...
  • Park_7677Park_7677 Missouri Member
    edited September 2003
    ;D
  • GHoosdumGHoosdum Icrontian
    edited September 2003
    :eek2: ... :hrm: ... ;D ... :thumbsup:
  • mmonninmmonnin Centreville, VA
    edited September 2003
    More L1 cache would be better. L2 has more latency than L1, why not have more. Lantency goes up from L1 to L2 to L3 up to RAM.
  • SimGuySimGuy Ottawa, Canada
    edited September 2003
    Enhanced Hyperthreading will be able to make-up for some of the inefficiencies with the longer pipeline of the Prescott CPU's.

    Intel is going to be using Asymmetric Hyperthreading technology on the Prescott, versus the current "Symmetric Hyperthreading" that has already been implemented on the P4 & Xeon processors.

    In Symmetric Hyperthreading, each virtual thread is treated as an equal. In Asymmetric Hyperthreading, the compiler would create "helper threads", which would assist the main virtual thread in completing complex calculations or in running subroutines, thereby speeding the overall Hyper-Threading process. The main thread wouldn't be bogged down while running the major calculations.

    What's it boil down to? Improved system performance and hyper-threading performance.

    Prescott will introduce 13 new instructions designed to improve the CPU's ability to deal with gaming and media applications. The new instructions will specifically address items such as floating-point to integer conversions, complex arithmetic and video encoding. Some of the 13 instructions will improve the performance of SSE technology, which is a set of process-level instructions that deals with and improves the performance of the SIMD (Single Instruction, Multiple Data) floating point. A few of the 13 instructions will be specific to improving HyperThreading and branch prediction.

    It would be nice to see Prescott increase the IPC of the CPU, but we all know that the NetBurst Microarchitecture of the P4 is designed for one thing: To scale nice and high.

    103W of heat dissipation? Eeek. Should be interesting to see the stock cooler that comes with this chip. Maybe Intel will finally start shipping a cooler that's all copper with an acceptable fan on it, not to mention doing away with the god awful thermal pad on the bottom of the stock heatsink and replacing it with at least some generic thermal transport compound.

    As well, Prescott-based motherboards will support a 250 MHz FSB speed that will be quad pumped to 1.00 GHz with the release of the new Socket. Yes, Intel's notoriously bad for switching sockets, but new CPU technology requires new support structures, especially where the Socket 423 -> 478 switch was concerned (Willamette, EWW).

    Should be interesting to see how the Prescott -vs- A64 showdown falls.

    //Edit: My spelling sucks. :D
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