PCI Express?
hub:
http://developer.intel.com/technology/pciexpress/devnet/
whitepaper:
http://developer.intel.com/technology/pciexpress/downloads/3rdGenWhitePaper.pdf
I was flipping through the Intel developer website today looking for information on PCI Express, which is supposedly going to be the next generation of graphics card interfaces. After reading the whitepaper, I noticed a couple problems however...
1) I don't see any way this will work natively (in described configurations) with the A64 or Opteron. The whitepaper makes it look like the PCI Express controller integrates the memory controller, graphics interface, and legacy PCI bridge, and then sits on the other side of the FSB from the CPU. The A64 doesn't have an external FSB, has the memory controller on the CPU, and communicates with the outside world via three HyperTransport lanes. In short, I can't figure out how PCI Express will talk to HyperTransport.
Hopefully the PCI Express I/O controller can be implemented as a HyperTransport node, but it looks like part of the speed gain from PCI Express comes from having a direct route from the memory to the graphics card or SCSI controllers or what have you, so I'm not sure how a PCI Express HT node would handle the equivalent of a DMA access (or even if it could).
2) I'm not liking the way they describe the mobile version. The nice thing about Cardbus was that it was just an extension of the 16-bit PCMCIA connector (added another row of pins). It'd suck to be the guy to find out your old 802.11 a/b/g card or mobile SCSI controller won't fit in the slot your new PCI Express notebook has.
I would like it very much if someone will prove me wrong.
-drasnor
http://developer.intel.com/technology/pciexpress/devnet/
whitepaper:
http://developer.intel.com/technology/pciexpress/downloads/3rdGenWhitePaper.pdf
I was flipping through the Intel developer website today looking for information on PCI Express, which is supposedly going to be the next generation of graphics card interfaces. After reading the whitepaper, I noticed a couple problems however...
1) I don't see any way this will work natively (in described configurations) with the A64 or Opteron. The whitepaper makes it look like the PCI Express controller integrates the memory controller, graphics interface, and legacy PCI bridge, and then sits on the other side of the FSB from the CPU. The A64 doesn't have an external FSB, has the memory controller on the CPU, and communicates with the outside world via three HyperTransport lanes. In short, I can't figure out how PCI Express will talk to HyperTransport.
Hopefully the PCI Express I/O controller can be implemented as a HyperTransport node, but it looks like part of the speed gain from PCI Express comes from having a direct route from the memory to the graphics card or SCSI controllers or what have you, so I'm not sure how a PCI Express HT node would handle the equivalent of a DMA access (or even if it could).
2) I'm not liking the way they describe the mobile version. The nice thing about Cardbus was that it was just an extension of the 16-bit PCMCIA connector (added another row of pins). It'd suck to be the guy to find out your old 802.11 a/b/g card or mobile SCSI controller won't fit in the slot your new PCI Express notebook has.
I would like it very much if someone will prove me wrong.
-drasnor
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Comments
-drasnor
http://www.chipzilla.org/?article=9264
-drasnor