Unlocked Hard-Locked AXPs? It may be possible...

ThraxThrax 🐌Austin, TX Icrontian
edited January 2004 in Hardware
<b>Read the intro and scroll to edit part two:</b>

It seems that mobile AXPs are free from clock hardlocks. Overclockers.ru theorizes that the multiplier table is sent to the L5 before being sent to all the places overclockers have traditionally been able to unlock their chips at.

It seems that by connecting the certain L5 bridges not only controls SMP/multi-lock, but also prevents the CPU multiplier lock to be transmitted throughout the CPU; which stops US. And when the chip is tricked into going mobile, the multi is free for change!

l6_02.gif

Rotating the table above 90* CCW, we have the real bridges:

l6_01.jpg

Can't hurt to try it guys. :)

Yes, I know that there are 5 bridges on the AXP and 4 in the diagram. I assume that it would be like this:

L6> . | | : | :

But you should also try:

L6> . : | | : |

To be sure.

If any of you have a Barton 2500, pull it and look at it: Is the last L6 closed, or second to last? That will tell us which four bridges are being shown in the table.

//EDIT:

There seems to be also some information discrepencies.

The L5 is listed in the table, the L6 is shown on the CPU picture.

We all know that the last L5 is the mod for SMP.. A ton of us have done it.

I need muddockter to tell us the status of his L5 bridges also, that could help us correlate the information into english (It's all currently russian).

I believe in the end that it was probably a mistake in OC.ru's picture, and we need to look at the L5.

//EDIT PART TWO:

The L5 controls the state of single CPU, SMP, or mobile.

L5> . | | : | <--- Mobile L5 state.

The L6 Controls the multipliers for a mobile athlon:

You can HARDCODE a multi, but it might be unnecessary. Here's an L6 table:

<DIV style="margin-right: 5px" class="left"><TABLE summary="mul1" class="data" width="270" border="1" cellspacing="0" cellpadding="3"><COL span="1" align="right"><COL span="3" align="center"><TR class="cap"><TD>Multiplier</TD><TD>Clock<BR>(FSB100)</TD><TD>L6-FID[4:0]</TD><TD>Model#</TD></TR><TR><TD> 5.0x</TD><TD> 500M</TD><TD>CC:CC</TD><TD> - </TD></TR>
<TR><TD> 5.5x</TD><TD> 550M</TD><TD>CC:C:</TD><TD> - </TD></TR>
<TR><TD> 6.0x</TD><TD> 600M</TD><TD>CC::C</TD><TD> - </TD></TR>
<TR><TD> 6.5x</TD><TD> 650M</TD><TD>CC:::</TD><TD> - </TD></TR>
<TR><TD> 7.0x</TD><TD> 700M</TD><TD>C:CCC</TD><TD> - </TD></TR>
<TR><TD> 7.5x</TD><TD> 750M</TD><TD>C:CC:</TD><TD> - </TD></TR>
<TR><TD> 8.0x</TD><TD> 800M</TD><TD>C:C:C</TD><TD> - </TD></TR>
<TR><TD> 8.5x</TD><TD> 850M</TD><TD>C:C::</TD><TD> - </TD></TR>
<TR><TD> 9.0x</TD><TD> 900M</TD><TD>C::CC</TD><TD> - </TD></TR>
<TR><TD> 9.5x</TD><TD> 950M</TD><TD>C::C:</TD><TD> - </TD></TR>
<TR><TD>10.0x</TD><TD> 1.0G</TD><TD>C:::C</TD><TD> - </TD></TR>
<TR><TD>10.5x</TD><TD>1.05G</TD><TD>C::::</TD><TD> - </TD></TR>
<TR><TD>11.0x</TD><TD>1.10G</TD><TD>CCCCC</TD><TD> - </TD></TR>
<TR><TD>11.5x</TD><TD>1.15G</TD><TD>CCCC:</TD><TD> - </TD></TR>
<TR><TD>12.0x</TD><TD>1.20G</TD><TD>CCC:C</TD><TD>1400FQQ3B</TD></TR><TR><TD>12.5x</TD><TD>1.25G</TD><TD>CCC::</TD><TD> - </TD></TR></TABLE></DIV>

<TABLE summary="mul2" class="data" width="270" border="1" cellspacing="0" cellpadding="3"><COL span="1" align="right"><COL span="3" align="center">
<TR class="cap"><TD>Multiplier</TD><TD>Clock<BR>(FSB100)</TD><TD>L6-FID[4:0]</TD><TD>Model#</TD></TR><TR><TD>13.0x</TD><TD>1.30G</TD><TD>:C:CC</TD><TD>1500FQQ3B</TD></TR><TR><TD>13.5x</TD><TD>1.35G</TD><TD>:C:C:</TD><TD> - </TD></TR>
<TR><TD>14.0x</TD><TD>1.40G</TD><TD>:C::C</TD><TD>1600FQQ3B</TD></TR>
<TR><TD class="text-yel">21.0x</TD><TD> - </TD><TD>:C:::</TD><TD> - </TD></TR>
<TR><TD>15.0x</TD><TD>1.50G</TD><TD>::CCC</TD><TD> - </TD></TR>
<TR><TD class="text-yel">22.0x</TD><TD> - </TD><TD>::CC:</TD><TD> - </TD></TR>
<TR><TD>16.0x</TD><TD>1.60G</TD><TD>::C:C</TD><TD> - </TD></TR>
<TR><TD>16.5x</TD><TD>1.65G</TD><TD>::C::</TD><TD> - </TD></TR>
<TR><TD>17.0x</TD><TD>1.70G</TD><TD>:::CC</TD><TD> - </TD></TR>
<TR><TD>18.0x</TD><TD>1.80G</TD><TD>:::C:</TD><TD> - </TD></TR>
<TR><TD class="text-yel">23.0x</TD><TD> - </TD><TD>::::C</TD><TD> - </TD></TR>
<TR><TD class="text-yel">24.0x</TD><TD> - </TD><TD>:::::</TD><TD> - </TD></TR>
<TR><TD> 3.0x</TD><TD> - </TD><TD>:CCCC</TD><TD> - </TD></TR>
<TR><TD class="text-yel">19.0x</TD><TD> - </TD><TD>:CCC:</TD><TD> - </TD></TR>
<TR><TD> 4.0x</TD><TD> - </TD><TD>:CC:C</TD><TD> - </TD></TR>
<TR><TD class="text-yel">20.0x</TD><TD> - </TD><TD>:CC::</TD><TD> - </TD></TR>
</TABLE><BR>
<P class="new"><B>C</B> = Closed , <B>:</B> = Open </P>

<b>THAT SAID</b>.. Making the chip a mobile might be enough for the 5Bit FID override or any l3/pin mod to work once more.


So to recap:

L6 controls mobile multis.
L5 might be in charge of multi hardlock.
Muddockter needs to look at his mobile Barton and tell us which bridges are connected on the L5.

Comments

  • fatcatfatcat Mizzou Icrontian
    edited December 2003
    interesting....here are some pics mudd had posted of his mobile 2400+...i dont have a digi-cam or i would take some pics of mine
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited January 2004
    We see that the L5 information is correct.

    l5 > | : | |

    WOOT.

    //EDIT:

    Does the mobile 2400 feature the same speeds as the desktop Athlon XP?

    //EDIT 2:

    Nevermind that.

    Someone want to take one of their locked chips and lock bridges according to the picture there?

    I think the L6 is irrelevant here unless people want to hardcode a multi.
  • pcscustompcscustom Oklahoma
    edited January 2004
    Hey thrax, Could you possibly draw a diagram for a newb? I have a 2600 i wouldnt mind trying.

    Trev
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited January 2004
    For the L5 bridges?

    Is it new packaging like you see in the pic of Mud's mobile, or old which is smooth?
  • fatcatfatcat Mizzou Icrontian
    edited January 2004
    Does the mobile 2400 feature the same speeds as the desktop Athlon XP?

    No... the 2400+ runs at 1.80ghz and has a FSB of 266...here are all the mobile speeds I know of

    Athlon XP-M 2500+ 1.87 266fsb 512k
    Athlon XP-M 2400+ 1.80 266fsb 512k
    Athlon XP-M 2200+ 1.80 266fsb 256k
    Athlon XP-M 2000+ 1.67 266fsb 256k
    Athlon XP-M 1700+ 1.47 266fsb 256k

    my 2400+m booted at 6x133...but all multis r unlocked
  • pcscustompcscustom Oklahoma
    edited January 2004
    New, Green.. I jus got it last week.

    Trev
  • pcscustompcscustom Oklahoma
    edited January 2004
    Well, I took the proc. out for a look, That looks like it isnt going to be easy but tomorro if I get out I will run by autozone and pick up a kit.. Hopefully i dont **** up too bad as this is my onyl running system atm.

    Trev
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited January 2004
    Just remember that the gold contacts you see are NOT the contacts to connect.

    The real contacts are the dark spots just in between the gold ones; you have to VERY VERY GENTLY scrape the packaging away to reveal those contacts, THEN seal the pit, then connect them.

    //EDIT:

    Realized the L6 table is correct too.

    Looks like we have all the facts we need.
  • qparadoxqparadox Vancouver, BC
    edited January 2004
    I'll ask my brother for permission to do his tomorrow. I have some old window defroster kit from the original athlon days (when pencil worked fine) but I think its a goner. Which is more recommended currently, window defroster or a trace pen?
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited January 2004
    Probably defroster; easier to remove.. I got lucky, though, and found a trace pen that's very durable, but scrapes off easily with a mildly firm pressure, some spit, and a thumbnail. ;D
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited January 2004
    Bump; this is potentially important.
  • muddocktormuddocktor
    edited January 2004
    Hey Thrax, I'm presently offshore but I should be coming back to the house in 2-3 more days as this well is winding up. When I get in I'll help out any way I can. I'm almost positive that the multi is being controlled by the L6 & L12 bridges on a mobile chip, in conjuction with software on the lappy because if you look at the pics of my mobile I posted, they show a hard coding of 6 on the L3 bridges, which is what my NF7-S boots it up at when installing the proc for the first time. The mobile 2400 is supposed to use a max multi of 14 at full speed, if I remember right, which would be the same as a 6 multi on the L3's except that the 5th L3 bridge (high sense bridge)would be open on a desktop proc for a 14 multi. If I hadn't just ordered an m0 stepping 2.4 P4 right before I left to come out here I would order a locked proc but the Pee4 tapped me out. :crazy:

    You might be on to something here, Thrax. :thumbup


    (Side note here) They have me set up next to the sat equipment out here and I tied into the 24 port switch on it so I have some communications, at least at night. :woowoo: ;D
  • BudBud Chesterfield, Va
    edited January 2004
    so is this is how they are suppost to be filled?
  • EQuitoEQuito SoCal, USA
    edited January 2004
    Bad news, I tried that on my locked Thorton and the CPU doesn't boot.
    Q: I left the FSB and cache mods intact, should I remove them and try again?
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited January 2004
    I would say that it's a possibility.

    I have this mod confirmed now on several tbreds by someone who can read the russian at overclockers.ru.
  • muddocktormuddocktor
    edited January 2004
    I'm wondering if you might have to also open up the first, third and fifth L6 bridges like the mobile procs have open also.
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited January 2004
    Well, no. The l6 bridge is mobile multiplier control. L1 and L3 are irrelevent to mobile chips as far as the multiplier is concerned.. First, third, and fifth bridges open corresponds to a 13.5 x 133 multiplier which equates to a 1.8GHz clockspeed, which is the correct mobile speed for a 2400M.
  • EQuitoEQuito SoCal, USA
    edited January 2004
    Thrax wrote:
    I would say that it's a possibility.

    I have this mod confirmed now on several tbreds by someone who can read the russian at overclockers.ru.
    but TBreds aren't locked so what are they testing? :scratch:
    I was hoping not to redo all my mods but I guess I'll have to... :(
    Oh well, anything in the name of OC'ing but not until tomorrow... :D
  • muddocktormuddocktor
    edited January 2004
    EQuito wrote:
    but TBreds aren't locked so what are they testing? :scratch:
    I was hoping not to redo all my mods but I guess I'll have to... :(
    Oh well, anything in the name of OC'ing but not until tomorrow... :D

    I read a few threads over at overclockers.com of late made Tbreds being locked also. I think they were made sometimes in the week 40-42 range.
  • ThraxThrax 🐌 Austin, TX Icrontian
    edited January 2004
    Tbreds are most certainly arriving locked.

    There's a littany of locked editions over at a forum which is keeping track of those locked; I'll have to remember where I saw it.
  • EQuitoEQuito SoCal, USA
    edited January 2004
    wow! I didn't know. That's some really bad news...
    ok, more testing tomorrow then.
  • pcscustompcscustom Oklahoma
    edited January 2004
    God damn.. Well anyway i attempted it and got an unknown proc at 12*180 and not budging... Wat did i do wrong?

    Trev
  • EQuitoEQuito SoCal, USA
    edited January 2004
    No luck guys...
    Deleted all mods, started from scratch on the L5's but the chip won't boot.
    I'll put it back to its original state and live with it... :(
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