Not surprising. Massively parallelized architectures don't use full execution engines for the cores... Some exclusive cache, an ALU, and a scheduler, and that's about it.
The fact that the company hasn't published a block diagram of their cores is more telling than anything. It's probably build on the SPARCv9 or ARM ISA, and the lack of FPU makes it absolutely useless for any scientific applications. It also makes it impossible to measure in FLOPs.
lordbean
Ontario, Canada
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The fact that the company hasn't published a block diagram of their cores is more telling than anything. It's probably build on the SPARCv9 or ARM ISA, and the lack of FPU makes it absolutely useless for any scientific applications. It also makes it impossible to measure in FLOPs.