PCM also ends the write endurance debate which continues to shroud NAND technology in a shadow of doubt. Because PCM uses the electrical resistance of matter states to represent binary data, it offers an unlimited number of write cycles.
What makes them think that the voltage application to change phases won't eventually wreck the phase changing mechanism, leading to the same cell degradation issues that affect NAND? Seems like the same kind of issues to me - or have I missed something?
Technically speaking, yes, it will eventually wreck the cells, but the earliest sample cells boasted 100,000,000 write cycles, or a 100x increase in even the most robust NAND cells with 20 years of R&D. Practically speaking, PRAM is no more limited than writing to a regular hard drive.
EDIT FOR CLARITY: 1,000,000 cycles is an SLC NAND endurance figure. Since PMC can store two bits per cell, it's similar to MLC NAND. Based on that metric, PMC is ~2857x more reliable.
Imagine the security implications of such a scenario, too.
At the OS level, they're no more than current suspend/hibernate scenarios. Requiring authentication on resume is pretty standard practice these days, at least in the business world (which is where any security concerns would be based to begin with).
As for the removing memory to read while the machine is offline, that's definitely something that will need to be addressed, and I'm sure it would be before they thought of pushing this technology out as a DRAM solution.
Outside of that, a 5nm process would allow for some phenomenal cell density. Once I can have my 2TB flash drive in my pocket, I'll be a very happy man.
The security risk of a non-volatile PRAM module is no different than the risk profile presented by a hard drive. Both require physical access and if that is your security breach, you already have bigger concerns than data theft.
The security risk of a non-volatile PRAM module is no different than the risk profile presented by a hard drive. Both require physical access and if that is your security breach, you already have bigger concerns than data theft.
Of course, this won't stop the same twonks that ran around like their hair was on fire when they discovered that under the correct (arguably super-extreme) conditions, you could read the RAM of a shut-down workstation/laptop.
Not entirely true, Rob. There have been proof-of-concept attacks where, for example, you freeze the RAM's ICs before they have a chance to lose their data. Doing so can get an enterprising hacker a RAM dump and get them an encryption key or various other gems hidden in memory. This removes the need for urgency - if the data stays there without freezing or various other extreme interventions, that data's there for anybody to dump.
I'm not saying that you could be safe even in the event of physical breaches, but it does make it theoretically easier.
Not entirely true, Rob. There have been proof-of-concept attacks where, for example, you freeze the RAM's ICs before they have a chance to lose their data. Doing so can get an enterprising hacker a RAM dump and get them an encryption key or various other gems hidden in memory. This removes the need for urgency - if the data stays there without freezing or various other extreme interventions, that data's there for anybody to dump.
I'm not saying that you could be safe even in the event of physical breaches, but it does make it theoretically easier.
His statement still holds true, though. If you've suffered a physical security breach (someone else has their hands on your hardware), you have other issues to deal with.
Of course, this won't stop the same twonks that ran around like their hair was on fire when they discovered that under the correct (arguably super-extreme) conditions, you could read the RAM of a shut-down workstation/laptop.
And my "not entirely true" references your mention that possessing the hard drive is the same end result of possessing non-volatile RAM and the hard disk. A disk alone, if encrypted well enough, could be safe. There are also ways around that, yes. But having a key stuck in memory just makes it easier and less destructive.
And again, my point was that this RAM erases the need for "arguably super-extreme" conditions to achieve the same result. That's all...
Byte-vs-block addressing is a function of how the storage device is built, not a limitation of the technology. Essentially all embedded devices using Flash MTDs use byte addressing. SSDs use block addressing because it allows them to be used with existing standard interfaces and filesystems.
This technology looks remarkably similar to phase-change shape memory alloys. When heated they switch from one crystalline configuration to another and switch back when cooled. The ones I've played with have latencies measurable in seconds but then again they weren't 40nm wide either.
Also, we've got to come up with a new acronym for this technology. PCM already has a definition in the context of computers and electronics. (pulse-coded modulation.)
By heating the chalcogenide to a temperature above its crystallization point, but below the melting point, it will transform into a crystalline state with a much lower resistance. The time to complete this phase transition is temperature-dependent. Cooler portions of the chalcogenide take longer to crystallize, and overheated portions may be remelted. Commonly, a crystallization time scale on the order of 100 ns is used. This is longer than conventional volatile memory devices like modern DRAM, which have a switching time on the order of two nanoseconds. However, a January 2006 Samsung Electronics patent application indicates PRAM may achieve switching times as fast as five nanoseconds.
You got me on the latency bit. I definitely mixed micro and nano-, however in terms of raw throughput, PRAM is faster than NAND and comparable to DRAM.
Thrax
🐌Austin, TX Icrontian
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What makes them think that the voltage application to change phases won't eventually wreck the phase changing mechanism, leading to the same cell degradation issues that affect NAND? Seems like the same kind of issues to me - or have I missed something?
Imagine the security implications of such a scenario, too.
Neat tech; been watching this for a while, but nice to see a breakthrough.
EDIT FOR CLARITY: 1,000,000 cycles is an SLC NAND endurance figure. Since PMC can store two bits per cell, it's similar to MLC NAND. Based on that metric, PMC is ~2857x more reliable.
At the OS level, they're no more than current suspend/hibernate scenarios. Requiring authentication on resume is pretty standard practice these days, at least in the business world (which is where any security concerns would be based to begin with).
As for the removing memory to read while the machine is offline, that's definitely something that will need to be addressed, and I'm sure it would be before they thought of pushing this technology out as a DRAM solution.
Outside of that, a 5nm process would allow for some phenomenal cell density. Once I can have my 2TB flash drive in my pocket, I'll be a very happy man.
Of course, this won't stop the same twonks that ran around like their hair was on fire when they discovered that under the correct (arguably super-extreme) conditions, you could read the RAM of a shut-down workstation/laptop.
I'm not saying that you could be safe even in the event of physical breaches, but it does make it theoretically easier.
His statement still holds true, though. If you've suffered a physical security breach (someone else has their hands on your hardware), you have other issues to deal with.
And again, my point was that this RAM erases the need for "arguably super-extreme" conditions to achieve the same result. That's all...
This technology looks remarkably similar to phase-change shape memory alloys. When heated they switch from one crystalline configuration to another and switch back when cooled. The ones I've played with have latencies measurable in seconds but then again they weren't 40nm wide either.
Also, we've got to come up with a new acronym for this technology. PCM already has a definition in the context of computers and electronics. (pulse-coded modulation.)
-drasnor
@Dras: PCM switches states in about 1µs. That's about 20x faster than DRAM's write latency.
via
Here's Numonyx's PCM whitepaper (PDF).
I've attached the relevant image.
-drasnor