Let's see how smart you are
Ok you overclockin' foos. Teach me. And no peeking at the BIOS optimization guide. What do each of these do and how should they be optimised? Or what happens when they are adjusted up/down? I know you guys have all this down pat.
Row Cycle Time (tRC)
Row refresh cyc time (tRFC)
RAS# to CAS# delay (tRCD)
Row to Row delay (tRRD)
Min RAS# active time (tRAS)
Row precharge time (tRP)
Write recovery time (tWTR)
Write to read dealy (tWTR)
Read to write delay (tRWT)
Refresh period (tREF)
Enagle 2T Timing
PCI Latency Timer (CLK)
Yup...I'm thinking about creating a guide/Reference guide to enhance performance via the whack of RAM settings and put a reader onto the better road to overclocking. So don't steal other people's writing.
Row Cycle Time (tRC)
Row refresh cyc time (tRFC)
RAS# to CAS# delay (tRCD)
Row to Row delay (tRRD)
Min RAS# active time (tRAS)
Row precharge time (tRP)
Write recovery time (tWTR)
Write to read dealy (tWTR)
Read to write delay (tRWT)
Refresh period (tREF)
Enagle 2T Timing
PCI Latency Timer (CLK)
Yup...I'm thinking about creating a guide/Reference guide to enhance performance via the whack of RAM settings and put a reader onto the better road to overclocking. So don't steal other people's writing.
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Probably the most concise guide I've seen thus far MM ...just in case you need references!!! rojakpot ...just scroll down and choose FREE Access to the BOG.
I'm looking forward to seeing what you come up with MM.
Data in a RAM module is stored in a data matrix. It has rows, and it has columns. That unique HEX address within windows that you see in the control panel if you poke around is the exact location of the row and column in which the data resides (Consequently, if you know hex to decimal conversion, you can locate the exact megabyte where a memory error occurs). Each point where a row and column intersects is called a memory block. Each side of the memory module is a bank. If the module has chips on both sides, it's double bank. If it has chips on one side, it's single bank.
Column Address Strobe (CAS):
This can typically be found as the CAS latency of a memory module. It is currently available in latencies 2, 2.5 and (Rarely) 3. This determines how fast that columns within the data-matrix may be accessed in integer cycles.
Row Address Strobe (RAS):
Found in integer values of 2, 3 and (rarely) 4. This is simply how fast the
system can access various rows inside the data-matrix at any given time. The same latency rules outlined above also apply here.
Timing Row/Column Determination (tRCD):
Also known as tRCD, this is the amount of time it takes for the memory to switch between accessing rows and columns. Memory is incapable of accessing both rows and columns simultaneously, so the lower that this value can achieve, the better.
Timing Precharge to RAS (tRP):
Also known as tRP, this determines how fast the memory can shift between data in either of its memory banks.
Access from Clock Time (tAC):
This is how quickly the memory can process data and put it as a burst over the system bus.
Clock Timing (tCLK):
This is simply the length of the clock cycle.
Row Cycle Time (tRC):
The tRC determines the lowest amount of clock cycles a memory row needs to complete. From the RAS, to tAC.
Row Refresh Cycle Time (tRFC):
I believe this determines the minimum duration in between tRC commands.
Row to Row Delay (tRRD):
The delay at which accessing sequential rows may be accomplished.
Active to Precharge (tRAS):
The time between activation of a memory row and tRP. This is particularly useful when the last row has been accessed and it needs to start anew, or a whole new memory address is being accessed.
Write Recovery Time (tWTR):
After a successful write to memory, tWTR values determine how quickly it can write again.
Write to Read Delay (tWTR):
After a successful write, and then a read command, this cycle time determines how quickly the memory can shift gears between reading and writing.
Read to Write Delay (tRWT):
The opposite of above. How quickly memory can begin to write after it has read.
Refresh period (tREF):
The interval (In nanoseconds) at which the memory can be electrically accessed. This determines the speed of the memory by the following equation:
1000/(ns), where NS stands for the nanosecond value of the refresh. For an example, Winbond and Samsung modules with a 5ns tREF are 200MHz DIMMs. 1000/5=200.
<b>All explanations from my memory guide originally written for www.icrontic.com, but never published.</b>