yeah should be pretty darn close, you'll also save on the power bill a bit with the single IIR my p3 power disappation tables correctly . Should be about 30 Watts less, which does add up.
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Geeky1University of the Pacific (Stockton, CA, USA)
edited December 2003
You guys are taking into account the fact that F@H is NOT smp-capable, right?
The P3-750s would take about 2x as long, but they'd be doing 2 WUs at once, too...
Folding is SSE-enhanced. When running an SSE-enabled application, SSE advantage scales with faster clock speed.
Therefore, the Celeron 1.3 @ 1.5 should fold slightly more efficiently and faster than the dual 750s.
One thing to keep in mind though... the Celeron only has 128 KB of L2 while the P3's have 256 KB (AFAIK), so that speed/efficiency advantage that the Celeron 1.5 has may be lost to the Dual P3's.
Straight answer? Probably in and around the same area, give or take a wee bit.
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Geeky1University of the Pacific (Stockton, CA, USA)
edited December 2003
Ok. I'll leave it alone for now, then. I'm getting restless... I have nothing to tweak (all my computers work *gasp*) so I'm trying to find something I can screw around with...
BTW, simguy, the Tualatin-core Celerons were P3s on a 100MHz bus; they had a full 256k of L2 cache.
Geeky1 had this to say Ok. I'll leave it alone for now, then. I'm getting restless... I have nothing to tweak (all my computers work *gasp*) so I'm trying to find something I can screw around with...
BTW, simguy, the Tualatin-core Celerons were P3s on a 100MHz bus; they had a full 256k of L2 cache.
I know the restlessness feeling. Everything here is working too good. I need something to explode/fail so I can troubleshoot. I'm getting ancy
Humm... then no doubt, the 1.5 Tualatin Celeron with the 256 KB L2 will fold faster than the 2 750's.
After reading the last few posts I guess the Celly would fold a lil bit faster. Not much tho. Plus it would take less power to run it like qparadox mentioned.
Comments
The Tualatin P3s (not the -S ones) and the Tualatin Celerons are basically identical, excpet for the bus speed.
The P3-750s would take about 2x as long, but they'd be doing 2 WUs at once, too...
Therefore, the Celeron 1.3 @ 1.5 should fold slightly more efficiently and faster than the dual 750s.
One thing to keep in mind though... the Celeron only has 128 KB of L2 while the P3's have 256 KB (AFAIK), so that speed/efficiency advantage that the Celeron 1.5 has may be lost to the Dual P3's.
Straight answer? Probably in and around the same area, give or take a wee bit.
BTW, simguy, the Tualatin-core Celerons were P3s on a 100MHz bus; they had a full 256k of L2 cache.
I know the restlessness feeling. Everything here is working too good. I need something to explode/fail so I can troubleshoot. I'm getting ancy
Humm... then no doubt, the 1.5 Tualatin Celeron with the 256 KB L2 will fold faster than the 2 750's.