Options
Pipeline changes could slow Prescott down
There are rumours circulating that Intel has re-engineered its Prescott architecture to include additional pipelines, which if true may well slow the chip down, not speed it up.
[blockquote]Intel is on record as saying in September that the Prescott, its forthcoming successor to the Northwood Pentium 4, as evolutionary and not revolutionary.
Northwood Pentium 4s have 20 stage pipelines, but double a number of critical resources including the L1 D-cache, the L1 I cache, the register re-name table, the and the branch prediction table.
If it does support any element of 64-bits, which again is still only speculation, that again would be doubling some registers and paths on the chips.
But it seems that the heat problems that the Prescott suffered from earlier this year has forced Intel to re-make the chips masks, with additional stages in the pipeline to get rid of the double clocking of the chip circuitry and the L1 cache decode.
[/blockquote]
[link=http://www.theinquirer.net/?article=13383]Read more[/link]
[blockquote]Intel is on record as saying in September that the Prescott, its forthcoming successor to the Northwood Pentium 4, as evolutionary and not revolutionary.
Northwood Pentium 4s have 20 stage pipelines, but double a number of critical resources including the L1 D-cache, the L1 I cache, the register re-name table, the and the branch prediction table.
If it does support any element of 64-bits, which again is still only speculation, that again would be doubling some registers and paths on the chips.
But it seems that the heat problems that the Prescott suffered from earlier this year has forced Intel to re-make the chips masks, with additional stages in the pipeline to get rid of the double clocking of the chip circuitry and the L1 cache decode.
[/blockquote]
[link=http://www.theinquirer.net/?article=13383]Read more[/link]
0
Comments
Intel - The people that'll walk 3 miles to get to a place only 2 miles away.
Those few Intel supporters hereabout would be running on the Tejas now if Intel hadn't been as inept with the 90nm process as they were the execution of the P4.
Why does adding pipelines allow the CPU to reach higher clockspeeds? Doesn't it add complexity, which would (at least logically) keep the CPU from reaching high clock speeds, because there's more to go wrong?
Two separate teams worked on the Hammer line and the AXP line.
That was always the gist I'd gotten from the scuttlebut I'd seen on the web.
I dunno why longer pipelines equal higher clock yeilds but that's the way it's seemed to work, Intel's northwood chips run twice the pipeline length as AMD's XP line and that's what's always credited with allowing the P4 to return higher clock speeds.
I guess I should've stayed in college after all...
Besides.. It's my turn to poke fun at Intel for massive delays!
The prescott was supposed to be out in June, and the Tejas is supposed to be here within the next two months.. But we won't see it until slightly under a year after it was supposed to happen.
Yeah, it's about the trip alright, how fast the trip is. But if Intel make a trip longer than it needs to be, it still takes longer than say, a more direct trip. Or for want of a better phrase, an AMD trip.
Am I talking c***? he he Pft! I'm just messing with anologies, don't mind me.
Sounds like a pretty water tight plan to me. I salute the very mention of the idea.
In a CPU, a pipeline is like a factory assembly line—it executes program instructions one stage at a time. The more stages there are in the pipeline, the less time each stage needs to complete its work, so the faster the CPU can cycle. While most CPUs have four to seven stages, and the Athlon is considered a superpipelined CPU with 10 stages, the P4 has more than 20 stages.
But superpipelines have drawbacks, which partly explains why a P4 doesn’t always perform as well as the clockspeed would indicate. Clock frequency is not an absolute measure of performance.
One drawback of superpipelines is the penalty they impose when the CPU must branch to another part of the program (Say.. Suddenly going from encoding a movie to loading plugins). Like an assembly line that must stop to change the kind of vehicle it’s manufacturing, a CPU pipeline must often pause to load a different stream of instructions. The deeper the pipeline, the greater the penalty during this switch. Modern processors try to avoid that penalty by using branch prediction units, and preloading registers that the CPU thinks it will have to use next.
So, by adding more stages to the pipeline, the CPU is allowed a higher speed because each stage needs less time to do the work, and when each stage needs less time to do the work, the clockspeed may rise because the demand on the pipeline isn't as high now.
Look at it this way: One assembly line has 10 steps to complete a car, and it has six minutes to build a car. That means each step may spend no longer than 36 seconds building. Each step needs exactly 36 seconds to build.. There's no room for extra efficiency, this line is assembling at maximum capacity.
Second assembly has 20 steps to build a car, and it must also do it in 6 minutes, and each step can take no longer than 18 seconds.. But here, because each step is so specialized, these steps only take 10 seconds. This line completes each car with 2 minutes and 40 seconds to spare.. Which allows them to send more cars down the line to assemble per day. But there's a problem in this one; the workers sometimes work so fast that there are errors, which may impede the next step, or the final product in total... So sometimes the cars have to be aborted and started over, thus diminishing the efficiency of this line, and reducing the 00:02:40 that this line has left to assemble. To compensate, this line has begun noticing when and where the errors go wrong in majority, and has started to predict where it needs parts to keep the errors under control.
But.. Even in the end; line two is still faster. If they added more steps to the assembly, it would reduce time per step, and increase the efficiency further.