The International Solid State Circuits Conference running February 8-12 in San Francisco will host a cadre of venerable tech firms, including Intel, which plans to discuss an octo-core Nehalem-based Xeon.
Evidence for the beastly CPU is revealed in item 3.1 on page 22 of the full conference itinerary (PDF):
Significant evidence adds veracity to the idea that this is indeed a Nehalem:
- An octo-core Penryn-based part would have an unworkable TDP. The Xeon X7460, a hexa-core chip based on Penryn architecture already claims a 130W TDP at just 2.66GHz. A higher envelope could easily be considered unsuitable given contemporary conventions for datacenter greenliness.
- A 6.4GT/s I/O lane smacks of the 6.4GT/s QuickPath Interconnect bus featured on today’s Nehalem processors. Given that QPI taps out around 7GT/s without the aid of phase changing, it’s unlikely that Intel has delivered a faster grade. That aside, the Penryn just doesn’t offer this kind of bus bandwidth.
- The transistor count is about right for an octo-core Nehalem. Today’s Bloomfield-based desktop Nehalem CPUs feature 731 million transistors with just 8MB lf L3 cache. Tripling the L3 cache to 24MB and doubling the core count spits out a 2,669,959,552 transistor chip. Tack on some architecture optimizations and some cache sharing, and you’re at a shiny 2.3 billion.
You can expect to see this chip known as the Beckton in the coming months. Chips based on this core will fit in a 90W, 105W or 130W TDP, use four QPI links (Bloomfield uses two), and rock FB-DIMM.
When all is said and done: we want.
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