Bobcat
Next on the launch deck is AMD’s “Bobcat” architecture, a chip explicitly designed to cater to roles currently overseen by chips like the Athlon Neo, VIA Nano and Intel Atom. According to the company’s roadmaps, the first chip to launch with Bobcat architecture will be the 32nm Ontario APU with two Bobcat cores and an entry-level DirectX 11 GPU.
AMD Bobcat architecture
Bobcat is another out-of-order processor which, like Bulldozer, dispatches threads from the frontend to a quad-pipe integer unit. Here, AMD has courteously provided additional detail: The ALU is broken down between two integer pipes, a load pipe, and a store pipe. Like Bulldozer, however, we do not know the number of stages cooked into these pipelines.
The Bobcat’s quad-pipe ALU is paired with a dual-pipe FPU, ambiguously titled “A-Pipe” and “M-Pipe” in this diagram. We postulate that the “A” and “M” refer to the FADD and FMUL/FDIV floating point ops, but the symmetry of the pipes is in question.
Jon Stokes of Ars Technica postulates that both pipelines support scalar double-precision floating point operations, while one is for SIMD permute ops, and the other is for SIMD scalar ops. From a simplicity standpoint—which Bobcat is all about—this design makes a lot of sense. Not baking both pipes with scalar and permute functionality certainly reduces floating point capability, but also reduces the complexity of the architecture through transistor reduction.
AMD claims that Bobcat is capable of <1W operation, which usually means 0.5W, but a chip running at that wattage could beat the Red October in a silent running contest. More practically, Bobcat’s actual TDP should be around 5-10W. That envelope means Bobcat is definitely for ultra portables—its performance won’t be high enough to touch big boy chips.
On the point of performance, AMD says it’ll weigh in at “90% of today’s mainstream performance” at less than half of the die size. If AMD’s definition of mainstream is the Athlon II—an assumption which bears out in their platform roadmaps—then Bobcat is essentially an Athlon II in a smaller, ultra mobile package. Not bad at all.
Bobcat’s most remarkable feature is not its architecture, however, but its design process. AMD has designed the Bobcat via high-level synthesis, or HLS. HLS is a process by which a chip’s design begins as an intended logic behavior written in a high-level language like C++; automated processes synthesize the behavioral blueprints into a physical hardware design which exhibits the intended behavior.
HLS is a fascinating way to rapidly design and produce a chip that can easily be modified or ported to other processes for outstanding flexibility in the market. The trade off for this agility is frequency—Bobcat’s maximum clockspeed with an HLS-driven design is about 20% lower than it could have been were it designed “by hand.”
All things considered, Bobcat will assuredly be faster than any ULV chip in the market today; it will handily eclipse the Nano, the Atom and the Athlon Neo, in many cases by orders of magnitude. Additionally, AMD’s decision to roll with HLS gives the firm the ability to respond to market conditions in ways its competitors simply cannot with current processes.
Though we cannot say what AMD’s competitors will cook up between now and the 2011 launch of Ontario, the firm is looking pretty solid here in 2009.
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